The Gigabit Link Interface Board (GLIB) is an evaluation platform and an easy entry point for users of high speed optical links in high energy physics experiments. Its intended use ranges from optical link evaluation in the laboratory to control, triggering and data acquisition from remote modules in beam or irradiation tests.
The GLIB is a double-width Advanced Mezzanine Card (AMC) conceived to serve a small and simple system residing either inside a μTCA crate or on a bench with a link to a PC and it is based on a high-performance Virtex-6 FPGA (XC6VLX130T). The GLIB can interface with four SFP+ transceiver modules, each operating at bi-directional data rates of up to 6.5Gbps. This performance matches comfortably the specifications of the GBT/Versatile Link project with its targeted data rate of 4.8Gbps. In its simplest form, one GLIB board thus interfaces with up to four GBT channels.
The GLIB I/O capability can be further enhanced with two FPGA Mezzanine Cards (FMCs).The two high-pin-count FMC sockets each provide up to 80 user-specific differential I/O pairs directly connected to the FPGA as well as two differential clock inputs and two differential clock outputs. The primary FMC also provides four optional 6.5Gbps transceiver lines, thus allowing extending the high speed serial I/O capability. Concerning the AMC high speed serial connectivity, the GLIB provides two Gigabit Ethernet (GbE) and two 2nd generation four-lane PCI Express (PCIe x4 GEN2) interfaces. It is important to mention that the GLIB gives users the possibility of implementing various other high speed serial data protocols (for custom applications) instead of PCIe. This is possible mainly thanks to GLIB’s sophisticated clock distribution circuitry that is based on cross-point switches and programmable clock multipliers. This circuitry offers a large selection of input clock sources (AMC clocks, FMC clocks, front panel clock connector or on-board oscillators).
The GLIB also carries a GbE PHY as well as an Ethernet plug in order to interface to a PC through a standard Ethernet cable, while in bench-top operation. For temporary data storage, two 72Mb SRAM devices are available on-board. It is important to note that the two SRAMs have independent address/data buses. For configuration purposes, a very flexible Joint Test Action Group (JTAG) circuitry based on a Complex Programmable Logic Device (CPLD) is also available. The CPLD acts as a JTAG switch selecting the JTAG master source between the dedicated JTAG connectors, MMC or AMC JTAG lines for the configuration of the FPGA and the associated EEPROM. The JTAG switch is also useful for boundary scan testing purposes.